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Preliminary Datasheet
LP78083
650mA High Efficiency Synchronous Buck with Dual Channel
General Description
The LP78083 are PMU, and contain a 650mA Buck DC/DC and dual channel 350mA Linear Regulator, Buck DC/DC is a constant frequency, current mode, PWM step-down converter. The device integrates a main switch and a synchronous rectifier for high efficiency. The 2.1V to 6.5V input voltage range makes the LP78083 is ideally suited for portable electronic devices that are powered from 1-cell Li-ion battery or from other power sources within the range such as cellular phones, PDAs and handy-terminals. Internal synchronous rectifier with low RDS(ON) dramatically reduces conduction loss at PWM mode. The internal synchronous switch increases efficiency while eliminate the need for an external Schottky diode.The switching ripple is easily smoothed-out by small package filtering elements due to a fixed operation frequency of 1.5MHz. This along with small 2*2 DFN-8 package provide small PCB area application. Other features include soft start, lower internal reference voltage with 2% accuracy, over temperature protection, and over current protection
LDO
Features
650mA Buck High Efficiency: 96%
1.5MHz Fixed-Frequency PWM Operation Adjustable Output From 0.6V to VIN 350mA LDO: 3.0V and 3.3V Fixed output 100% Duty Cycle Low Dropout Operation Available in 2*2 TDFN-8 Package Low than 1A Shutdown Current
Applications
Portable Media Players/MP3 players Cellular and Smart mobile phone PDA DSC Wireless Card
Pin Configurations
Ordering Information
LP78083 - / F: Pb-Free Package Type QV: SOT23-6 Out3 Voltage Type 30: 3.0V 33: 3.3V Out2 Voltage Type 30: 3.0V 33: 3.3V
LP78083 - Ver. 1.0 Datasheet Feb.-2008
PIN NO 1 2 3 4 5 6 7 8
Function SW GND OUT2 VIN OUT3 EN VDD FB1
Marking Information
Please see website.
Page 1 of 8
Preliminary Datasheet Typical Application Circuit
VIN 4 7 6 OUT3 Vin VDD EN FB SW 1 2.2uH OUT1
LP78083
8
LP78083
5 GND OUT3 OUT2 3
OUT2
Figure 1. LP78083 High Efficiency Step-Down Converter
Functional Pin Description
Pin Number 1 2 3 4 5 6 7 10 Pin Name SW GND OUT2 VIN OUT3 EN VDD FB Pin Function Ground. Pin For Switching Output2,LDO output Power Input. Output3,LDO output DC/DC Chip Enable(Active High). Power Input. Feedback Input Pin, Reference voltage is 0.6 V
Function Block Diagram
LP78083 - Ver. 1.0 Datasheet
Feb.-2008
2
Page 2 of 8
Preliminary Datasheet Absolute Maximum Ratings

LP78083
-0.3V to 6V 350mA 800mA 800mA 1100mA --40 to 85 125 --65 to 150 260 2KV
Input Supply Voltage LDO Current P-Channel Switch Source Current(DC) N-Channel Switch Current(DC) Peak SW Sink and Source Current Operation Temperature Range Junction Temperature Storage Temperature Lead Temp(Soldering,10sec) ESD Rating(HBM)
Electrical Characteristics
(VIN = 3.6V, VOUT = 2.5V, VREF = 0.6V, L = 2.2H, CIN= 4.7F, COUT= 10F, TA= 25C, IMAX = 600mA unless otherwise specified) Parameter Input Voltage Range Quiescent Current Shutdown Current Reference Voltage Adjustable Output Range Symbol VIN IQ ISHDN VREF VOUT VOUT VOUT Output Voltage Accuracy Fixed VOUT VOUT VOUT VOUT VOUT VIN = 2.2 to 5.5V, VOUT = 1.2V 0A < IOUT < 650mA VIN = 2.2 to 5.5V, VOUT = 1.5V 0A < IOUT < 650mA VIN = 2.2 to 5.5V, VOUT = 1.8V 0A < IOUT < 650mA VIN = 2.8 to 5.5V, VOUT = 2.5V 0A < IOUT < 650mA VIN = 3.5 to 5.5V, VOUT = 3.3V 0A < IOUT < 650mA VIN = VOUT + 0.2V to 5.5V, VIN 3.5V 0A < IOUT < 650mA VIN = VOUT + 0.4V to 5.5V, VIN 2.2V 0A < IOUT < 650mA IOUT = 0mA, VFB =0.5V IOUT = 0mA, VFB =0.7V EN = GND For adjustable output voltage 0.602 VREF -3 -3 -3 -3 -3 -3 -3 300 IOUT = 200mA IOUT = 200mA VIN =2.2 to 5.5V VIN = 3.6V VIN = 3.6V Test Conditions Min 2.5 270 25 0.1 0.612 Typ Max 5.5 350 35 1 0.622 VIN - 0.2 +3 +3 +3 +3 +3 +3 +3 Units V uA uA V V % % % % % % % mA
Adjustable LDO Output current PMOSFET RON NMOSFET RON P-Channel Current Limit EN Threshold EN Leakage Current ILDO
350
0.45 0.45
400 0.53
PRDS(ON) NRDS(ON)
IP(LM)
VEN VENL
600
0.8 --
800
1.2 2
1000
1.5
mA
V uA
LP78083 - Ver. 1.0 Datasheet
Feb.-2008
Page 3 of 8
Preliminary Datasheet Typical Operating Characteristics
LP78083
LP78083 - Ver. 1.0 Datasheet
Feb.-2008
Page 4 of 8
Preliminary Datasheet Applications Information
The basic LP78083 application circuit is shown in Typical Application Circuit. External component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by CIN and COUT. Inductor selection The output inductor is selected to limit the ripple current to some predetermined value. typically 20%~40% of the full load current at the maximum input voltage. Large value inductors lower ripple currents. Higher Vin or VOUT also increases the ripple current as shown in equation. A reasonable starting point for setting ripple current is IL=180mA(40% of 650mA).
LP78083
series resistance(ESR) that is required to minimize voltage ripple and load step transients, an well as the amount or bulk capacitance that is necessary to ensure that the control loop is stable. Loop stability can be checked by viesing the load transient response as described in later section.the output ripple, VOUT, is determined by:
Using ceramic input and output capacitors Higher values, lower cost ceramic capacitors are now becoming .Available in smaller case sizes ,their high ripple current ,high voltage rating and low ESR make them ideal for switching regulator applications. however care must be taken when these capacitors are used at the input and output. When a ceramic capacitor is use at input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input ,VIN, At worst,a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part.
The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 720Ma rated Inductor should be enough for most applications (650mA+120mA). For better efficiency, choose a low DC-resistance inductor. CIN and COUT Selection The input capacitance, CIN ,is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple voltage, a low ESR input capacitor Sized for the maximum RMS current should be used. RMS current is given by:
Output voltage programming The output voltage is set by a resistive divider according to the Following formula:
The external resistive divider is connected to the output, allowing Remote voltage sensing as shown in figure3.
This formula has a maximum at VIN=2VOUT, where IRMS=IOUT/2.this simple worst-case condition is commonly.Used for design because even significant deviations do not offer much relief. Note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the Capacitor, or choose a capacitor rated at a higher temperature Than required. Several capacitors may also be paralleled to meet size or height requirements in the design.
The selection of COUT is determined by the effective
LP78083 - Ver. 1.0 Datasheet
Feb.-2008
Page 5 of 8
Preliminary Datasheet
Efficiency considerations
The efficiency of a switching regulator is equal to the output Power divided by the input power times 100%.it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement efficiency can be expressed as : Efficiency= 100%- (L1+L2+L3...) Where L1L2, etc. are the individual losses as a percentage of Input power .although all dissipative elements in the for most of losses: VIN quiescent current and 12R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence.
LP78083
2. 12Rlosses tae calculated from the resistances of the internal switches, RSW and external inductor RL. in continuous mode the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the LX pin is a function of both top and bottom MOSFER RDS(ON) and the duty cycle (DC) as follows: RSW=RDS(ON)TOPxDC+RDS(ON)BOTx(1-DC) The RDS(ON) for both the top and bottom MOSFETS can be obtained from the typical performance characteristics curves. thus, to obtain 12R losses, simply add RSW to RL and multiply the square of the average output current.
Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% of the total loss.
1.The VIN quiescent current is due to two components: the DC Bias current as given in the electrical characteristics and the Internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power MOSFET switches .Each time the gate charge current.results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switches from high to low to high again, a packet of charge Q moves from VIN to ground.
The resulting Q/t is the current out of VIN that is typically larger than the DC bias current. In continuous mode. LGATCHG=f(QT+QB) Where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages.
LP78083 - Ver. 1.0 Datasheet
Feb.-2008
Page 6 of 8
Preliminary Datasheet Checking Transient Response
LP78083
The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ILOAD (ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem.
Layout Considerations
Follow the PCB layout guidelines for optimal performance of LP78083. For the main current paths as indicated in bold lines, keep their traces short and wide. Put the input capacitor as close as possible to the device pins (VIN and GND). LX node is with high frequency voltage swing and should be kept small area. Keep analog components away from LX node to prevent stray capacitive noise pick-up. Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the LP78083. Connect all analog grounds to a command node and then connect the command node to the power ground behind the output capacitors.
LP78083 - Ver. 1.0 Datasheet
Feb.-2008
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Preliminary Datasheet Packaging Information
LP78083
LP78083 - Ver. 1.0 Datasheet
Feb.-2008
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